Power semiconductor devices are roughly divided into two types: a lateral semiconductor device in which electrodes are formed on one side and a current flows in a horizontal direction, and a vertical semiconductor device in which electrodes are formed on both sides and a current flows in a vertical direction. Examples of the vertical semiconductor device include a planar gate n-channel vertical metal-oxide-semiconductor field effect transistor (MOSFET). Hereinafter, the planar gate n-channel vertical MOSFET is also referred to as a vertical MOSFET.
In the vertical MOSFET, an n-type drift layer having high-resistance serves as a region that, in an on state, allows a drift current to flow in the vertical direction, and, in an off state, causes a depletion layer to widen in the vertical direction under application of a reverse bias voltage. When a current path of the n-type drift layer is shortened, that is, a thickness of the n-type drift layer is reduced, a drift resistance is lowered, thereby allowing a substantial on-resistance of the vertical MOSFET to be reduced. However, a width of a drain-to-source depletion layer stretched from a p-n junction formed between a p-type well region and the n-type drift layer is reduced, thereby causing a critical electric field intensity of the semiconductor to be reached at a relatively low voltage and thus causing a substantial breakdown voltage of the vertical MOSFET to decrease. In contrast, when the thickness of the n-type drift layer is increased, the breakdown voltage of the vertical MOSFET increases, but the on-resistance of the vertical MOSFET increases, and thus a loss as a semiconductor element increases. As described above, a trade-off relationship exists in principle between the on-resistance and the breakdown voltage of the vertical MOSFET. The trade-off relationship also applies to semiconductor devices other than a MOSFET such as an insulated gate bipolar transistor (IGBT), a bipolar junction transistor (BJT), a schottky barrier diode (SBD), and a p-intrinsic-n (PiN) diode.
As a technique for solving in principle the above-described trade-off relationship, a semiconductor device having a structure based on a super junction technique is known, the structure based on a super junction technique corresponding to a parallel p-n structure in which the drift layer is divided into an n-type drift region and a p-type pillar region, both of the regions having high concentration, and the n-type drift region and the p-type pillar region are alternately and repeatedly bonded in the horizontal direction (for example, refer to Non-Patent Documents 1 and 2). Hereinafter, the structure based on a super junction technique is referred to as a super junction (SJ) structure.
In the semiconductor device having the super junction structure, even when both the n-type drift region and the p-type pillar region in the parallel p-n structure have high concentration, in the off state, a depletion layer is stretched in the horizontal direction from each p-n junction extending in the vertical direction of the parallel p-n structure to cause the entire drift layer to be depleted, which achieves both low on-resistance and high breakdown voltage.
Further, as a semiconductor material used for a power semiconductor device, silicon carbide (hereinafter referred to as SiC) instead of conventional silicon (hereinafter referred to as Si) has attracted attention. A semiconductor device formed of SiC is capable of high-speed operation and high-temperature operation with low on-resistance, that is, low loss as compared with a semiconductor device formed of Si. This is because SiC has excellent material physical properties as a semiconductor material. Specifically, SiC has a large band gap of about 3 eV and can be used extremely stably even at high temperatures. A dielectric breakdown electric field of SiC is one order of magnitude larger than a dielectric breakdown electric field of Si, which achieves low on-resistance.
SiC is expected to be applied particularly to a MOSFET among power semiconductor devices in the future as a semiconductor material having a high possibility of exceeding a physical limit of Si. Specifically, great expectations have been placed on an SiC-SJ-MOSFET that achieves both low on-resistance and high breakdown voltage. Herein, the SiC-SJ-MOSFET refers to a MOSFET having the super junction structure using SiC. Note that, in the following description, the SiC-SJ-MOSFET and the Si-SJ-MOSFET are collectively referred to as an SJ-MOSFET.
The typical SiC-SJ-MOSFET is similar in cross-sectional structure to the Si-SJ-MOSFET. In the SJ-MOSFET, breakdown voltage and avalanche resistance are influenced by not only a structure of a region where the MOSFET operates actively, but also a structure of a region provided around a cell region. Therefore, it is required that the structure of the cell region and the structure of the edge termination region of the SJ-MOSFET be appropriately designed. Note that the avalanche resistance refers to an energy that a semiconductor device withstands without being destroyed when a voltage exceeding a maximum rating is applied to the device. Further, a region where the MOSFET operates actively is referred to as a cell region, an activated region, an effective region, an active region, an element region, or the like, and is hereinafter typically referred to as a cell region. A region provided around the cell region is referred to as an edge termination region, a peripheral region, a junction edge termination region, an element peripheral region, or the like, and is hereinafter typically referred to as an edge termination region.
Conventionally, a semiconductor device is disclosed in which a p-type region is formed on a surface portion adjacent to a source electrode and all p-type pillar regions and the p-type region in an edge termination region are electrically connected (for example, refer to Patent Document 1). Here, the p-type region is referred to as a RESURF layer, a junction termination extension (JTE), a depletion layer extending layer, or the like, and is hereinafter typically referred to as a RESURF layer. In the semiconductor device disclosed in Patent Document 1, when a high voltage is applied to the drain electrode, the depletion layer is surely expanded to an edge of the device, which achieves higher breakdown voltage. That is, stable higher breakdown voltage is achieved not only in the cell region but also in the edge termination region by formation of the cell region and the edge termination region in the super junction structure and formation of the RESURF layer in the edge termination region.